The present invention relates to a multi-way interleave-type semiconductor device testing apparatus in which a plurality of test circuit units each having the same circuit configuration are provided and these test circuit units are operated in interleaved manner, thereby to permit the testing apparatus to test semiconductor devices at high speed.
FIG. 7 shows an example of the semiconductor device testing apparatus (hereinafter referred to as IC tester) for testing, for example, a semiconductor integrated circuit (hereinafter referred to IC) which is a typical example of the semiconductor devices. The illustrated IC tester TES comprises, mainly, a main controller 30, a pattern generator 10, a timing generator 31, a waveform shaping device 32, a waveform generator 33, a group of drivers 1, a group of level comparators 3, a logical comparator 9, a failure analysis memory 34, and a device power supply 35.
The main controller 30 is generally constructed by a computer system, and mainly controls the pattern generator 10 and the timing generator 31 in accordance with a test program PM created by a user. Although not shown, the timing generator 31 generally comprises a period generator, a clock control circuit, and a clock generator.
First, before a testing for ICs is started, various kinds of data are set in the IC tester from the main controller 30. After the various kinds of data have been set, a testing for ICs is started. By a test start instruction or command applied to the pattern generator 10 from the main controller 30, the pattern generator 10 starts to generate a pattern. Accordingly, the time point that the pattern generator 10 starts to generate a pattern becomes the time point of starting a testing. The pattern generator 10 supplies test pattern data to the waveform shaping device 32 and at the same time, supplies timing set information (which is also called timing set data) TS to a period generator and a clock generator, both of which are not shown, of the timing generator 31.
The timing set information means a pair of one information for selecting period data previously set in a period data memory of the period generator and another information for selecting clock data previously set in a clock data memory of the clock generator. The timing set information is previously programmed by a user.
By application of the timing set information TS to the timing generator 31, the timing generator 31 generates a timing signal (clock pulse) for controlling timings of operation of the waveform shaping device 32, the logical comparator 9 and the like.
The test pattern data outputted from the pattern generator 10 in synchronism with the period data of the period generator is converted to a test pattern signal having a real waveform by the waveform shaping device 32 and the waveform generator 33 located at the succeeding stage of the waveform shaping device 32. The test pattern signal is applied to an IC under test (commonly called DUT) 2 through a group of the drivers 1 to store it in the memory of the IC under test 2.
On the other hand, a response signal read out of the IC under test 2 is compared in a group of the level (analog) comparators 3 with a reference voltage from a comparison reference voltage source (not shown) to determine whether or not the response signal has a predetermined logical level (a voltage of H logical level (high logical level), or a voltage of L logical level (low logical level)). A response signal which has been determined to have the predetermined logical level is sent to the logical comparator 9 where the response signal is compared with an expected value signal (data) outputted from the pattern generator 10.
When the response signal does not coincide with the expected value signal, the memory cell of the IC under test 2 at the address thereof from which that response signal has been read out is determined to be defective or a failure, and a failure (FAIL) signal is generated indicating that the memory cell read out of the IC under test 2 is failure, and is stored in the failure analysis memory 34. Usually, the failure signal is stored in a memory cell of the failure analysis memory 19 having the same address as that of the IC under test 20.
On the contrary, when the response signal coincides with the expected value data, the memory cell of the IC under test at the address thereof from which that response signal has been read out is determined to be normal, and a pass signal indicating that the memory cell read out of the IC under test 2 is not defective is generated. Usually, this pass signal is not stored in the failure analysis memory 34. At the time of completion of the test, the failure signals stored in the failure analysis memory 34 are read out thereof to determine, for example, whether the failure memory cell or cells of the tested IC 2 can be relieved or not.
As discussed above, the timing generator 31 generates, in accordance with the timing set information TS given from the pattern generator 10, timing signals (clock pulses) for defining a rising timing and a falling timing of the waveform of a test pattern signal which is to be applied to an IC under test 2, timing signals (clock pulses) for a strobe pulse defining a timing of the logical comparison in the logical comparator 9, and the like.
Timings and periods for generating those timing signals are written as timing set information in the test program PM created by a user, and the IC tester is arranged such that a test pattern signal is applied to an IC under test 2 with an operating period or duty cycle and at a timing intended by a user to operate the IC under test 2, and that whether the operation of the IC under test 2 is proper or not can be tested.
As shown in FIG. 7, a semiconductor device testing apparatus having one timing generator 31, one pattern generator 10, one waveform shaping device 32, and one logical comparator 9 provided therein, and wherein a test pattern signal is generated using a timing signal (clock pulses) outputted from the one timing generator 31 to test the semiconductor device under test is called one-way system testing apparatus in this technical field.
On the contrary, a semiconductor device testing apparatus having a plurality of basic test circuit units provided therein, each basic test unit comprising one timing generator 31, one pattern generator 10, one waveform shaping device 32, and one logical comparator 9, and wherein timing signals (clock pulses) outputted from the timing generators of the plurality of basic test circuit units are multiplexed, and the plurality of basic test circuit units are operated in interleaved manner using the multiplexed timing signals to generate a test pattern signal, thereby to test a semiconductor device under test is called a multi-way interleave-type testing apparatus in this technical field (the interleave operation of the plurality of basic test circuit units means that the plurality of basic test circuit units are sequentially operated within one cycle (one period) at timings shifted a little by a little from one another, that is, the plurality of basic test circuit units are operated in parallel manner within one cycle).
A semiconductor memory having a clock synchronous type interface (a device of synchronous type) such as a synchronous DRAM (a synchronous dynamic RAM) has a function for delaying an output cycle of data therein, and by setting the number of cycles to be delayed in a register within the memory, the memory can output an input data thereinto with a delay corresponding to the number of cycles set in the register. The number of cycles to be delayed is called latency in this technical field.
In case of testing such a synchronous type device in a semiconductor device testing apparatus, it is necessary to delay an expected value signal (EXP) and a comparison enable signal (CPE) outputted from a pattern generator by a latency set in the device under test. For this reason, there is provided between a pattern generator and a logical comparator a pattern delay circuit in which a delay time (the number of cycles to be delayed) corresponding to the latency set in the device under test is set, thereby to delay an expected value signal and a comparison enable signal to perform a logical comparison.
FIG. 8 shows an example of the conventional two-way interleave-type IC tester which is constructed such that synchronous type devices can also be tested. Since this IC tester adopts a two-way interleave-type, there are provided in the IC tester a set of the aforementioned basic test circuit units (each comprising the timing generator 31, the pattern generator 10, the waveform shaping device 32, and the logical comparator 9). The IC tester is arranged such that these two basic test circuit units (a first test circuit unit 4-1 and a second test circuit unit 4-2) are alternately operated (operated in interleave manner or interleaved in operated) in one cycle (one period) to generate a test pattern signal S1 to be applied to the IC under test 2 at high rate, and also to read out a response signal S2 from the IC under test 2 at high rate to perform a logical comparison, so that the test for the IC under test 2 can be carried out at high speed. Further, since the first and the second test circuit units 4-1 and 4-2 have the same circuit configuration with each other, the circuit configuration of the second test circuit unit 4-2 is not shown in FIG. 8. However, the components, signals and data of the first test circuit unit 4-1 will be shown by adding xe2x80x9c1xe2x80x9d after a hyphen (-) to their reference characters, and also the components, signals and data of the second test circuit unit 4-2 will be shown by adding xe2x80x9c2xe2x80x9d after a hyphen (-) to their reference characters.
In order to make it possible to test a synchronous type device, the first and the second test circuit units 4-1 and 4-2 further comprise pattern delay circuits 6-1 and 6-2 (6-2 is not shown), respectively, and also delay setting registers 5-1 and 5-2 (5-2 is not shown) for setting a delay time (the number of cycles to be delayed) corresponding to the latency set in the IC under test 2 in the pattern delay circuits 6-1 and 6-2, respectively. The pattern delay circuit 6-1 is connected between the pattern generator 10-1 and the logical comparator 9-1. The pattern delay circuit 6-2 is connected between the pattern generator 10-2 (not shown) and the logical comparator 9-2 (not shown). Further, the period generator and the clock control circuit in the timing generator 31, and the waveform shaping device 32 in the test circuit unit shown in FIG. 7 are unnecessary components here, and those components have been removed from FIG. 8. In addition, in order to simplify the explanation, portions and elements in FIG. 8 corresponding to those in FIG. 7 are shown by the same reference characters affixed thereto and the explanation thereof will be omitted unless it is necessary.
In the two-way interleave-type IC tester shown in FIG. 8, the pattern generators 10-1 and 10-2 are alternately operated, and test pattern data outputted as a result of the alternate operation are converted to a test pattern signal S1 having a real waveform by waveform shaping devices (not shown) and a waveform generator (not shown). This test pattern signal S1 is applied to the IC under test 2 via the driver group 1. A response signal S2 read out from the IC under test 2 is compared in the level comparator group 3 with a reference voltage Vr from the comparison reference voltage source (not shown) to determine whether the response signal S2 has a predetermined logical level (a voltage of H logic (high logic) or a voltage of L logic (low logic)) or not. The response signal determined to have the predetermined logical level is converted to a logical signal S3 which is in turn sent to the timing comparators 8-1 and 8-2 (8-2 is not shown). The logical signal S3 supplied to the timing comparators 8-1 or 8-2 is then strobed by a strobe signal STRB-1 or STRB-2 (STRB-2 is not shown) outputted from the clock generator 7-1 or 7-2 (7-2 is not shown) of the timing generator (not shown). Generally, a response signal S2 having the predetermined H logic is converted to a logical xe2x80x9c1xe2x80x9d signal and a response signal S2 having the predetermined L logic is converted to a logical xe2x80x9c0xe2x80x9d signal, respectively, in the level comparator group 3.
Logical signals S4-1 and S4-2 (S4-2 is not shown) their timings of which are defined by the strobe signals STRB-1 and STRB-2 respectively are supplied to the logical comparators 9-1 and 9-2. In the case that the IC under test is not a synchronous type device, the logical signals S4-1 and S4-2 are logically compared with expected value signals (data) EXP-1 and EXP-2 (EXP-2 is not shown) outputted from the pattern generators 10-1 and 10-2, respectively.
If the comparison result thereof indicates an anticoincidence, a failure signal (FAIL) is generated by each of the logical comparator 9-1 and 9-2, and the failure signal is stored in the associated failure analysis memory (not shown). Generally, as a failure signal is generated a logical xe2x80x9c1xe2x80x9d signal which is stored in the same address of the failure analysis memory as that of the IC under test 2. On the contrary, if the comparison result thereof indicates a coincidence, a pass signal (PASS) is generated by each of the logical comparator 9-1 or 9-2. Usually, the pass signal is not stored in the failure analysis memory. Further, in FIG. 8, the failure signals and/or the pass signals outputted from the logical comparators 9-1 and 9-2 are shown by reference characters FAIL/PASS-1 and FAIL/PASS-2, respectively.
In the case that the IC under test is a synchronous type device, the expected value signals EXP-1 and EXP-2 as well as the comparison enable signals CPE-1 and CPE-2 (CPE-2 is not shown) outputted from the pattern generators 10-1 and 10-2 respectively are delayed in the pattern delay circuits 6-1 and 6-2 by a delay time (the number of cycles to be delayed) corresponding to the latency set in the IC under test 2, and are supplied to the logical comparators 9-1 and 9-2, respectively. The logical signals S4-1 and S4-2 are logically compared with these delayed expected value signals EXP-1xe2x80x2 and EXP-2xe2x80x2 (EXP-2xe2x80x2 is not shown), respectively. In this case, likewise, if the comparison result thereof indicates an anticoincidence, a failure signal (FAIL) is generated by each of the logical comparator 9-1 or 9-2 and the failure signal is stored in the associated failure analysis memory. If the comparison result thereof indicates a coincidence, a pass signal (PASS) is generated.
Since the IC tester shown in FIG. 8 is a two-way interleave-type one, the operating period (cycle) of each of the first and the second test circuit units 4-1 and 4-2 is two times the test period (called rate) of the IC tester. As a result, as shown in FIGS. 10 and 11, the clock generators 7-1 and 7-2 generate period signals PS-1 and PS-2 respectively each having its period of two times the test period Tr of the IC tester, as well as generate strobe signals STRB-1 and STRB-2 respectively each having its period of two times the test period Tr of the IC tester. In addition, the clock generator 7-2 of the second test circuit unit 4-2 generates the period signal PS-2 and the strobe signal STRB-2 at the time point (timing) delayed respectively by the test period Tr of the IC tester from the period signal PS-1 and the strobe signal STRB-1 of the clock generator 7-1 of the first test circuit unit 4-1. In this case, however, since the clock setting value Tc for setting timings of clocks generated from the clock generators 7-1 and 7-2 is set to a value by which the strobe signals STRB-1 and STRB-2 are generated at intermediate points of the test period Tr of the IC tester respectively, the strobe signals STRB-1 and STRB-2 are generated from the clock generators 7-1 and 7-2 with a delay time corresponding to the clock setting value Tc from the period signals PS-1 and PS-2, respectively. In other words, the strobe signals STRB-1 and STRB-2 are pulse signals which can be obtained by delaying the period signals PS-1 and PS-2 by the time interval corresponding to the clock setting value Tc.
FIG. 10 is a timing chart in the case that the expected value signals EXP-1 and EXP-2 as well as the comparison enable signals CPE-1 and CPE-2 outputted respectively from the pattern generators 10-1 and 10-2 are not delayed by the pattern delay circuits 6-1 and 6-2, respectively. FIG. 10A is a timing chart for the first test circuit unit 4-1, FIG. 10B is a timing chart for the second test circuit unit 4-2, and FIG. 10C is a timing chart for explaining the comparison operations in the IC tester. FIG. 11 is a timing chart in the case that the expected value signals EXP-1 and EXP-2 as well as the comparison enable signals CPE-1 and CPE-2 outputted respectively from the pattern generators 10-1 and 10-2 are delayed by the pattern delay circuits 6-1 and 6-2, respectively, by one cycle, namely, a time interval corresponding to the two times the test period Tr of the IC tester. FIG. 11A is a timing chart for the first test circuit unit 4-1, FIG. 11B is a timing chart for the second test circuit unit 4-2, and FIG. 11C is a timing chart for explaining the comparison operations in the IC tester. Further, in those drawings, it is assumed that each of the expected value signals EXP-1 and EXP-2 as well as each of the comparison enable signals CPE-1 and CPE-2 are outputted, in the first test circuit unit 4-1, from the pattern generator 10-1 in the sequence of logical xe2x80x9c1xe2x80x9d, logical xe2x80x9c0xe2x80x9d, logical xe2x80x9c1xe2x80x9d, . . . , and is outputted, in the second test circuit unit 4-2, from the pattern generator 10-2 in the sequence of logical xe2x80x9c0xe2x80x9d, logical xe2x80x9c1xe2x80x9d, logical xe2x80x9c0xe2x80x9d, . . . .
As can be understood easily from FIGS. 10 and 11, in the first test circuit unit 4-1, with regard to the expected value signal EXP-1, the first half of each cycle thereof corresponding to one of odd periods (1), (3), (5), . . . among the successive test periods Tr of the IC tester is logically compared in the timing comparator 8-1 with a logical signal S4-1 which is strobed by a strobe signal. STRB-1, whereas in the second test circuit unit 4-2, with respect to the expected value signal EXP-2, the first half of each cycle thereof corresponding to one of even periods (2), (4), (6), . . . among the successive test periods Tr of the IC tester is logically compared in the timing comparator 8-2 with a logical signal S4-2 which is strobed by a strobe signal STRB-2. In other words, with respect to the expected value signals EXP-1 and EXP-2, the first half of each cycle of the expected value signal EXP-1 and the first half of each of the expected value signal EXP-2 are logically compared with logical signals S3 alternately outputted with the test period Tr of the IC tester from associated one level comparator of the level comparator group 3. Therefore, each of the logical signals S3 outputted from the level comparator group 3 is logically compared in the logical comparators 9-1 and 9-2 with the expected value signal at high rate with the test period Tr of the IC tester, i.e., with 1/2 of the period of the expected value signal or the strobe signal.
In FIG. 11, since the latency of the IC under test 2 is 2, a response signal S2 from the IC under test 2 is outputted with a delay time of two test periods (2xc3x97Tr). Accordingly, a logical signal S3 outputted from each of the level comparator group 3 is also delayed by two test periods. On the other hand, since the strobe signals STRB-1 and STRB-2 occur with no delay time, as shown in FIG. 11C, the first strobe pulses in these strobe signals STRB-1 and STRB-2 have no relation to the strobe operation, respectively, which does not bring about any problems at all. Since the delay amount for each of the pattern delay circuits 6-1 and 6-2 is set to one cycle corresponding to the latency equal to 2, the expected value signals EXP-1 and EXP-2 are delayed by one cycle and are supplied to the logical comparators 9-1 and 9-2 as expected value signals EXP-1xe2x80x2 and EXP-2xe2x80x2, respectively. Therefore, with respect to the expected value signals EXP-1xe2x80x2 and EXP-2xe2x80x2, their respective first half cycles are, at the time point delayed by one cycle further from the case of FIG. 10, logically compared alternately with the logical signals S4-1 and S4-2 strobed respectively by the strobe signals STRB-1 and STRB-2 with the period of the IC tester, respectively. As a result, the logical signal S3 outputted from each of the level comparator group 3 with the delay time of two times the test period is also logically compared with the expected value signals EXP-1xe2x80x2 and EXP-2xe2x80x2 with the test period Tr of the IC tester.
Further, as shown in FIG. 8, the IC tester may be constructed such that the failure/pass signals FAIL/PASS-1 and FAIL/PASS-2 outputted from the logical comparators 9-1 and 9-2 respectively may be inputted to an OR gate 11 if necessary, and be outputted from the OR gate 11 as the sum signal FAIL/PASS logically added one with the other.
Since the pattern delay circuits 6-1 and 6-2 each for delaying an expected value signal and a comparison enable signal by the desired number of cycles have the same circuit configuration with each other, FIG. 9 shows, as a typical example thereof, the pattern delay circuit 6-1 of the first test circuit unit 4-1. This pattern delay circuit 6-1 comprises a delay circuit 6a for the expected value signal EXP-1 and a delay circuit 6b for the comparison enable signal CPE-1. Each of the delay circuits 6a and 6b comprises a shift register 12 constituted by D-type flip-flops (D-F/F) of n stages connected in series (n=7 in FIG. 9) and a selector 13 (in this example, 8-1 selector) for selecting either one of the input and the output signals of each stage of the D-type flip-flops.
A period signal (clock pulse) PS-1 having its period of 2Tr is supplied, as a shift pulse, from the clock generator 7-1 to the D-type flop-flops at respective stages of the shift register 12. Accordingly, each of the D-type flip-flops delays the expected value signal/comparison enable signal EXP-1/CPE-1 by one cycle. On the other hand, to a select terminal SEL of the selector 13 is supplied a delay setting value (an amount of delay corresponding to a latency of the IC under test 2) to be set in the delay setting register 5-1. Accordingly, if the latency of the IC under test 2 is assumed to be N, N/2 is set in the delay setting register 5-1. Consequently, the selector 13 selects the output of the D-type flip-flop at the (N/2)-th stage from the input side of the shift register. As a result, the selector 13 outputs an expected value signal/a comparison enable signal EXP-1xe2x80x2/CPE-1xe2x80x2 which are delayed by 2Trxc3x97(N/2)=Trxc3x97N from the inputted expected value signal/comparison enable signal EXP=1/CPE-1 respectively.
As mentioned above, in the case of delaying an expected value signal/a comparison enable signal outputted from each of the pattern generators 10-1 and 10-2 by the desired number of cycles, the prior art IC tester uses such circuit configuration that the number of cycles of the expected value signal/comparison enable signal to be delayed is set in the respective delay setting registers 5-1 and 5-2 of the first and the second test circuit units 4-1 and 4-2, and this number of delay cycles is supplied to the pattern delay circuits 6-1 and 6-2, thereby to delay the expected value signal/comparison enable signal.
However, as discussed above, since the operating period (one cycle) of each of the first and the second test circuit units 4-1 and 4-2 is two times the test period Tr of the IC tester, each period of the expected value signals EXP-1, EXP-2 and the comparison enable signals CPE-1, CPE-2 outputted respectively from the pattern generators 10-1 and 10-2 is 2xc3x97Tr and on the other hand, since the IC under test 2 is tested based on the test period (one test cycle) Tr of the IC tester, a test pattern signal is applied to the IC under test with the test period Tr. Therefore, one test cycle of the IC under test 2 becomes 1/2 of one cycle of the expected value signal/comparison enable signal.
For the above-mentioned reasons, in the prior art IC tester, the value of 1/2 (N/2) of the latency N of the IC under test 2 is set in the delay setting registers 5-1 and 5-2, and the delay amount (the number of cycles to be delayed) corresponding to the set value N/2 is set in the pattern delay circuits 6-1 and 6-2, thereby to delay the expected value signals/comparison enable signals. Specifically speaking, as shown in FIG. 8, nxe2x88x921 delay amount setting lines D0, D1, . . . , Dnxe2x88x922 are connected from the output sides of the delay setting registers 5-1 and 5-2 to the pattern delay circuits 6-1 and 6-2, respectively, and when the latency N of the IC under test 2 is 0, N/2=0 (no delay amount) is set in the delay setting registers 5-1 and 5-2. As a result, data indicating that the delay amount is 0 is sent to the pattern delay circuits 6-1 and 6-2 via the delay amount setting lines D0, D1, . . . , Dnxe2x88x922. When the latency N of the IC under test 2 is 2, N/2=1 (which means that only one cycle is to be delayed) is set in the delay setting registers. As a result, data indicating that the delay amount is one cycle is sent to the pattern delay circuits 6-1 and 6-2 via the delay amount setting lines. Further, when the latency N of the IC under test 2 is 4, N/2=2 (which means that two cycle is to be delayed) is set in the delay setting registers. As a result, data indicating that the delay amount is two cycles is sent to the pattern delay circuits 6-1 and 6-2 via the delay amount setting lines. Thereafter, similar operations are repetitively performed.
Consequently, the prior art IC tester has a drawback that if the latency N of the IC under test 2 is an odd number, the number of cycles to be delayed cannot be set in the delay setting registers 5-1 and 5-2. In other words, the prior art IC tester of two-way interleave-type could not test synchronous type devices unless the latency N thereof is an even number.
Similarly, in a three-way interleave-type IC tester, the test period Tr of an IC under test becomes 1/3 of the period of each of the expected value signal/comparison enable signal or the strobe signal, and hence N/3 which is the value of 1/3 of the latency N of the device under test is set in the delay setting register of each of the test circuit units. Therefore, the prior art three-way interleave-type IC tester cannot test a synchronous type device unless the latency N thereof can be divided by 3 without any remainder.
In other words, in the prior art multi-way interleave-type IC testers, there is a serious drawback that they cannot test synchronous type devices unless the latency N thereof can be divided by the number of interleaves m without any remainder, that is, unless N/m becomes an integer.
It is an object of the present invention to provide a multi-way interleave-type semiconductor device testing apparatus which is capable of testing a semiconductor device under test even if the latency of the semiconductor device is either an even number or an odd number.
In order to accomplish the above object, in an aspect of the present invention, there is provided a semiconductor device testing apparatus in which a test pattern signal is produced on the basis of test pattern data outputted from a pattern generator and is applied to a semiconductor device under test, and a response signal outputted from the semiconductor device under test is logically compared with an expected value signal outputted from the pattern generator, thereby to determine whether the semiconductor device under test is defective or not defective, and comprising a plurality of test circuit units each comparing a response signal from the semiconductor device under test with an expected value signal from the pattern generator, the plurality of test circuit units being sequentially operated within one cycle thereby effecting logical comparisons at high rate, and wherein each of the plurality of test circuit units comprising: a clock generator for generating a period signal representing an operating period of associated one test circuit unit; a delay setting register in which a latency N is set, said latency N being the number of cycles that an output of a semiconductor device under test is to be delayed; a pattern delay circuit connected to the output side of said delay setting register via a required number of data transmission lines and for delaying the expected value signal by a time interval obtained by multiplying numerical value data transmitted from the delay setting register by the operating period; clock control means connected to the output side of said delay setting register via a required number of data transmission lines and for selecting, in response to numerical value data transmitted from the delay setting register, one of plural timing setting values to supply the selected timing setting value to the clock generator, each of said plural timing setting values setting a timing of generation of the period signal generated from the clock generator; and means for logically comparing a response signal from the semiconductor device under test with an expected value signal from the pattern delay circuit.
In a first preferred embodiment, the number of the test circuit units are two, and the clock control means comprises: adding means for adding up a test period Tr of the semiconductor device testing apparatus and a clock setting value Tc in which a timing of generation of the period signal generated from the clock generator has been preset; and a selector having a select terminal to which the least significant bit line among the data transmission lines is connected and for selecting the clock setting value Tc when the least significant bit line is xe2x80x9c0xe2x80x9d, and selecting the sum Tc+Tr of the clock setting value and the test period which is the output of the adding means when the least significant bit line is xe2x80x9c1xe2x80x9d. All higher bit lines among the data transmission lines except the least significant bit line are connected to the pattern delay circuit.
The pattern delay circuit delays the expected value signal by a delay time obtained by multiplying transmitted numerical value data by the test period.
In a second preferred embodiment, the clock control means comprises: a multiplier for multiplying numerical value data transmitted via the data transmission lines by a test period Tr of the semiconductor device testing apparatus; and adding means for adding up an output from the multiplier and a clock setting value Tc in which a timing of generation of the period signal generated from the clock generator has been preset. The number of interleave m is further set in the delay setting register, and the integer part of the quotient resulting from a division of the latency N by the number of interleaves m is transmitted to the pattern delay circuit via the data transmission lines. The pattern delay circuit delays the expected value signal by a delay time obtained by multiplying the transmitted numerical value data by the test period.
In a modified embodiment, the delay setting register transmits the latency N and the number of interleaves m to the pattern delay circuit via the data transmission lines. The pattern delay circuit takes out, from the latency N and the number of interleaves m transmitted thereto, the integer part of the quotient resulting from a division of N by m, and delays the expected value signal by a delay time obtained by multiplying the integer part by the test period.
The plurality of test circuit units may use one delay setting register in common.